This invention relates to a semiconductor memory device having a multibank memory structure adapted to an increase in memory capacity.
Following an increase in memory capacity, use has recently been made of a semiconductor memory device having a multibank memory structure.
Referring to FIG. 1, an existing semiconductor memory device of the type comprises a plurality of banks B0, B1, . . . , and Bn. In order to reduce a circuit area, an input/output bus connected to an input/output block is often divided into a plurality of local buses L0, L1, . . . , and Ln arranged in the banks B0, B1, . . . , and Bn, respectively, and a global bus G connected to the local buses L0, L1, . . . , and Ln.
Referring to FIG. 2, each of the banks B0 through Bn includes a plurality of memory cells. In the bank B0, the memory cells C00, C01, . . . , and C0n are arranged at junctions between a plurality of word lines WL00, WL1, . . . , and WL0n and a pair of digit lines D0 and DB0. In the bank B1, the memory cells C10, C11, . . . , and C1n are arranged at junctions between a plurality of word lines WL10, WL11, . . . , and WL1n and a pair of digit lines D1 and DB1. The bank B0 further includes a sense amplifier SA0 and a pair of read/write control transistors TR01 and TR02 connected to output sides of the digit lines D0 and DB0. The bank B1 further includes a sense amplifier SA1 and a pair of read/write control transistors TR11 and TR12 connected to output sides of the digit lines D1 and DB1. Although not illustrated in the figure, each of the remaining banks has a similar structure.
The existing semiconductor memory device further comprises a plurality of transfer gates TRF1, TRF2, . . . , and TRFn arranged at junctions between the local buses L0, L1, . . . , and Ln and the global bus G.
In the existing semiconductor memory device described above, the local buses L0, L1, . . . , and Ln and the global bus G are connected through the transfer gates TRF1, TRF2, . . . , and TRFn, respectively. With this structure, a capacitance of the global bus G is included in a load upon each of the sense amplifiers SA0, SA1, . . . , and SAn during a reading operation of the memory cells. Thus, when each of the sense amplifiers SA0, SA1 . . . , and SAn is driven, the load including the capacitance of the global bus is inevitably imposed. It is therefore difficult to shorten a sensing time.